The present invention disclosed herein relates to semiconductor devices and methods of forming the same, and more particularly, to semiconductor devices having a convex active region and methods of forming the same.
Generally, a field effect transistor (FET) includes an active region, a gate electrode crossing over the active region and source/drain electrodes formed adjacent to the gate electrode. The active region under the gate electrode is used as a channel region that provides a moving path for charges between source/drain regions formed in the active region on respective sides of the gate electrode. In other words, the channel region is the active region between the source and drain electrodes.
As the integration density of semiconductor devices increases, the widths of the gate electrodes and active regions have generally been reduced. However, as the width of the gate electrode is reduced, a length of the channel region (i.e., a space between the source region and the drain region) is also reduced. If the width of the active region is reduced, the width of the channel region may also be reduced, which may cause a narrow width effect that generally decreases a drain current.
In recent years, to address technical problems, including the short channel effect or the narrow channel effect, a fin-FET having a fin-shaped active region has been proposed. In the fin-FET, as a facing area between the gate electrode and the channel region is increased, the channel width can be increased, in comparison with a planar FET, and an electric potential of the channel region can be effectively controlled.
However, in a typical conventional fin-FET, a conductive residue may be formed between gate electrodes, which may result in a gate bridge phenomenon. More specifically, FIGS. 1A and 1B are perspective views illustrating the gate bridge occurring in a conventional method of fabricating a fin-FET.
Referring to FIGS. 1A and 1B, a device isolation pattern 20 is formed on a predetermined region of a semiconductor (integrated circuit) substrate 10 to define active regions 15. The device isolation pattern 20 is recessed to expose a top surface and upper portions of sidewalls (hereinafter, referred to as upper sidewalls) of the active regions 15. A gate insulating layer 25 is formed on the top surface and the upper sidewalls of the exposed active regions 15. A gate conductive layer 30 is formed on the semiconductor device in the region where the gate insulating layer 25 is formed.
As seen in FIG. 1B, the gate conductive layer 30 is patterned to form gate patterns 35 crossing over the active regions 15. The forming of the gate patterns 35 includes etching the gate conductive layer 30 until the top surfaces of the device isolation pattern 20 and the active regions 15 are exposed.
Due to a height difference between the active regions 15 and the device isolation pattern 20, a deposition thickness h1 of the gate conductive layer 30 is smaller than a vertical thickness h2 of the gate conductive layer 30 at the side of the active regions 15. Due to this thickness difference, a conductive residue 50 electrically connecting the gate patterns 35 to each other may be formed on the side surfaces of the active regions 15 as a result of the etching process used in patterning the gate conductive layer 30. The conductive residue 50 may cause defects, such as the gate bridge.
A conventional floating gate type flash memory device may have various technical problems caused by increasing an aspect ratio of a gate pattern in high-density devices. To address such problems, a charge trap (floating gate) type nonvolatile memory device has been proposed, which includes a tunneling insulating layer (interposed between the active region and the gate electrode), a charge storage layer, and a blocking dielectric layer. However, due to the increase of the aspect ratio of a gap region with the high integration devices, it is generally necessary to reduce the thickness of the blocking dielectric layer. If the thickness of the blocking dielectric layer is not reduced, the facing area between the gate pattern and the charge storage layer may be reduced by the blocking dielectric layer filling an upper portion of the gap region. However, reducing the thickness of the blocking dielectric layer may cause problems with an electrical property of the memory cell, which may be deteriorated due to leakage current.